1. Field of the Invention
The present invention is directed to integrated circuit design software used in the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to managing data path crossings between synchronous and asynchronous clock domains in integrated circuit design.
2. Description of the Prior Art
Current methods for synchronizing data path crossings between asynchronous clock domains in an integrated circuit design generally require that a designer manually generate false path timing constraints or add synchronizers to a data path in the RTL code. A false path is a term used in static timing analysis (STA) that indicates that the timing from a certain start point to a certain end point in a path is not valid (false) and therefore is not required to satisfy timing closure. For example, a path is false if it is not possible to generate a timing violation on the path due to the logic associated with the path.